1. Field of the Invention
The present invention relates to a process for producing a circuit board. In particular, the present invention relates to a process for efficiently producing a thin circuit board with high-density interconnections.
2. Description of the Related Art
FIG. 11A to 12F are each a process drawing of an example of a known circuit board (see Japanese Unexamined Patent Application Publication No. 2004-235323).
In FIG. 11A, a supporting substrate 10 includes a copper-clad laminate in which copper foil 11 is bonded on the front surface and the back surface of a resin plate 10a. 
Dummy metal layers 41 are bonded to both surfaces of the supporting substrate 10 with adhesive layers 40. Two-layer metal laminates 43, which are larger than the dummy metal layers 41, are bonded to the surfaces of the supporting substrate 10 at peripheries of the dummy metal layers 41 with the adhesive layers 40 so as to cover the dummy metal layers 41 (see FIG. 11B). The two-layer metal laminates 43 each include a copper layer 42; and a metal layer 42a composed of nickel, titanium, or chromium, which is not etched with an etching solution for copper, the metal layer 42a being disposed on the copper layer 42.
As shown in FIG. 11C, a laminate 50 in which interconnection patterns 44 are laminated with insulating layers 46 provided therebetween and are electrically connected to each other using vias 48 is formed on each two-layer metal laminate 43 by a buildup method.
As shown in FIG. 11D, the laminates 50 and the supporting substrate 10 are cut at inner positions compared with the periphery of each dummy metal layer 41 to separate each dummy metal layer 41 from the corresponding two-layer metal laminate 43 to detach the laminates 50.
As shown in FIG. 12A, the copper layer 42 of each two-layer metal laminates 43 is removed by etching using the metal layer 42a as a barrier layer.
As shown in FIG. 12B, the metal layer 42a is removed by etching.
The laminate 50 is inverted (see FIG. 12C). Patterns 52 each composed of a solder resist are formed on the front surface and the back surface of the laminate 50 (FIG. 12D). The exposed interconnection pattern 44 is plated with nickel and then gold using the pattern 52 as a mask to form protective plating layers 54 (FIG. 12E). Solder bumps 56 are formed on predetermined positions to complete the circuit board (FIG. 12F).
In the known method for producing a circuit board as shown in FIG. 11C, all of the interconnection patterns 44 in the laminates 50 are formed on the metal layers 42a by a buildup method. In the buildup method, the copper layers are formed by plating, which requires a prolonged period of time, and etched by etching to form the patterns. Thus, such pattern formation disadvantageously requires a prolonged period of time. In particular, a larger number of laminated layers requires a more prolonged period of time.